Akeana 100 Series Processors
The Akeana 100 Series of processors is highly configurable and customizable, supporting applications from embedded microcontrollers to edge gateways and personal compute devices.
The Akeana 100 Series is optimized for ultra-small size and low power applications, with a short, In-Order pipeline length and In-Order execution 32-bit RISC-V architecture. A range of memory system configurations with cache to CCM blocks makes the Akeana 100 Series ideal for real-time computation applications.
The Akeana 100 Series is the entry-level product in Akeana’s three processor lines, offering customers one of the broadest processor IP portfolios. Start your journey today with one or more of these Akeana processors.
Up to 64 KB Data and Instruction Caches
Up to 512 KB Data and lnstruction Closely-Coupled Memory (CCM)
Physical Memory Protectlon Unit
32-bit Physical Addresses
Akeana 100 Series Processor Diagram
Akeana 100 Series Standard Configurations
| Basic Akeana 100 Core Configuration | Product | Standard Features | Typical Applications |
|---|---|---|---|
| L1 I-cache: 8 KB/core RV32IMAC_Zicsr_Zifencei_Zicbo instruction set Up to 32 bits Physical Address range | Akeana 110 | 4-stage, in-order pipeline Single-width instruction issue ICCM: 16 KB/core DCCM: 16 KB/core |
|
| L1 I-cache: 16 KB/core RV32IMAC_Zicsr_Zifencei_Zicbo instruction set Up to 32 bits Physical Address range Physical Memory Protection (PMP) with 8 entries | Akeana 120 | 5-stage, in-order pipeline Single-width instruction issue ICCM: 64 KB/core DCCM: 64 KB/core | Area- and power-constrained microcontroller |
| Akeana 130 | 9-stage, in-order pipeline Dual instruction issue ICCM: 64 KB/core DCCM: 64 KB/core Branch predictor Secondary ALU for enhanced performance | Microcontroller |
|
| Akeana 140 | 9-stage, in-order pipeline Dual instruction issue L1 D-cache: 16 KB/core ICCM: 512 KB/core DCCM: 512 KB/core Branch predictor Secondary ALU for enhanced performance | Enhanced Performance Microcontroller |
Add-On Options Include
- L1 Instruction cache, up to 128 KB
- L1 Data cache, up to 64 KB
- Instruction Closely-Coupled Memory (ICCM) 0 to 512 KB
- Data Closely-Coupled Memory (DCCM) 0 to 512 KB
- Physical Address width 32 bits
- Scalar Cryptographic (Zk) extension
- Packed SIMD extension (P)
- Physical Memory Protection (PMP) , 1 to 8 regions
- Custom instructions
