Akeana 1000 Series Processors
The Akeana 1000 Series of processors is highly configurable and customizable, supporting applications from smart homes and wearables, to automotive ADAS applications.
These processors can be configured with support for 1-, 2-, or 4-way Multi-threading.
The Akeana 1000 Series is optimized for a broad range of applications, available with either an In-Order or Out-of-Order microarchitecture and from single-issue to quad-issue instruction issue width, to provide customers with the range needed for a variety of computation requirements.
The Akeana 1000 Series is the midrange of Akeana’s three processor product lines, offering customers one of the broadest available processor IP portfolios. Start your journey today with one or more of these Akeana processors.
9-stage in-order or 12-stage out-of-order pipeline
MMU with up to
512-entry,
4-way TLB
Multi-threaded architecture support
Up to 4-wide issue architecture supported
Akeana 1000 Series Processor Diagram
Akeana 1000 Series Standard Configurations
| Basic akeana 1000 Core Configuration | Product | Standard Features | Typical Applications |
|---|---|---|---|
| RV64GCB_Zicbo instruction set Full RVA22 RISC-V Profile Single- & double- precision floating-point User Mode Supervisor Mode 48 bits Virtual Address range 39 bits Physical Address range Scalable to fully coherent many core clusters ECC support AXI/ACE (512 bits) Physical memory Protection (PMP) with 16 entries MU | Akeana 1100 | 9-stage, in-order pipeline Dual instruction dispatch L1 I-cache: 16 KB/core L1 D-cache: 16 KB/core MMU with 256-entry, 4 way TLB | High-end microcontroller |
| Akeana 1200 | 9-stage, in-order pipeline 3-way instruction dispatch Secondary ALU in pipeline L1 I-cache: 32 KB/core L1 D-cache: 32 KB/core MMU with 256-entry, 4-way TLB | Edge gateway |
|
| Akeana 1300 | 12-stage, out-of-order pipeline 4-way instruction dispatch L1 I-cache: 32 KB/core L1 D-cache: 32 KB/core L2 cache: 256KB MMU with 512-entry, 4-way TLB | Edge gateway, "Little" core in Big/Little configurations |
Add On Options Include
- L1 Instruction cache, up to 128 KB
- L1 Data cache, up to 64 KB
- L2 cache, up to 1 MB
- Physical Address width 32 to 39 bits
- Virtual Address width 39, 48, or 57 bits
- Shared, unified Last-Level Cache (LLC), up to 16 MB
- Scalar Cryptographic (Zk) extension
- Hypervisor (H) extension
- Vector (V) extension (64 to 512 bits)
- Vector Cryptographic (Zvk) extension
- Physical Memory Protection (PMP) , up to 64 regions
- TLB up to 2048 entries, 8 ways
- Custom instructions
- Support for 2-way or 4-way multithreaded microarchitecture
