Processor System IP

The Compute Coherency Block (CCB) connects a cluster of up to 8 cores coherently, using a directory-based protocol. The CCB also includes a cache that is shared by the core cluster. This localized coherency domain can interface with the non-coherent Interconnect or coherent Interconnect IP using the industry standard AMBA AXI (non-coherent) or CHI (coherent) protocols, respectively. The CCB provides RAS support in the form of ECC/parity protected caches with error reporting along with asynchronous interfaces for DVFS functionality.

The software programmable IOMMU from Akeana is compliant with the RISC-V architecture. It provides the capability to translate device physical addresses to system physical addresses to optimize and protect shared SOC memory from external device DMA.

AMBA AXI is a compatible Interconnect Fabric that provides the capability to interconnect multiple Akeana cores. This is Akeana’s Interconnect IP that enables customers to quickly implement a non-coherent multi-core solution.

An AMBA CHI compatible Coherent Interconnect Fabric that provides the capability to coherently interconnect multiple CCBs to construct many-core compute configurations. It provides the building blocks to coherently manage the multiple CCB instances with additional shared cache.

Akeana provides all the IP for all interrupt control and management. These include the RISC-V APLIC (advanced platform-level interrupt controller), the RISC-V ACLINT (advanced core level interrupt controller), as well as the IMSIC (incoming message signaled interrupt controller) to handle both wired and MSIs.